1. Field of the Invention
The present invention relates in general to a semiconductor device and in particular to a resistance element formed of polycrystalline silicon and used in semiconductor integrated circuits or the like.
2. Description of the Prior Art
In static memory integrated circuits, for example, a resistance element is formed of polycrystalline silicon.
In the case of a static memory cell shown in FIG. 1, load resistances R1 and R2 formed of polycrystalline silicon (hereinafter referred to as Poly Si in an abridgement) and exhibiting a high resistance not smaller than 10.sup.8 ohms (.OMEGA.) are connected between a power supply source V.sub.DD and insulated gate field effect transistors (hereinafter referred to as MOS transistors) T.sub.r1 and T.sub.r2, respectively. Specifically, these resistances are achieved by using a wiring 21 formed of Poly Si which is divided into a high resistance part 22 realized by low impurity ion implantation and a low resistance part 23 realized by high impurity diffusion or the like process, as can be seen from FIGS. 2 and 3 which show a wiring conductor in a plan view and a sectional view, respectively. In FIG. 3, reference numeral 31 denotes a silicon dioxide (SiO.sub.2) film, 32 denotes a phospho silicate glass (PSG) film and 33 denotes a silicon (Si) substrate. The resistance value of polycrystalline silicon or Poly Si resistance elements can be controlled to a desired value in a range of 10.sup.5 .OMEGA. to 10.sup.12 .OMEGA., for example, which value is controllably determined by the impurity dose implanted through the ion implantation. Leakage current through the MOS transistors T.sub.r1 and T.sub.r2 is compensated by a small current flowing through the high resistance Poly Si element 22, whereby information is held as stored in the memory cell. Accordingly, it is very important to control the small current flowing through the high resistance Poly Si element. In FIG. 1, numeral 11 denotes a word line, and 12 denotes a data line.
The Poly Si resistance element suffers from a drawback that the resistance value thereof is undesirably decreased when the resistance element undergoes treatments such as formation of protection films for interconnection layers in succession to the formation of aluminium (Al) metallization layers and then subjected to thermal processes such as hydrogen annealing and cerdip (glass molding) at a temperature of about 450.degree. C. By way of example, a curve 41 shown in FIG. 4 illustrates how the resistance value of Poly Si resistance element is decreased due to the hydrogen (H.sub.2) annealing process. It should be noted, however, that the rate of decrease in the resistance value is usually so small that the resistance value will remain without departing appreciably from a standard value.
Recently, a development has been made in resin molding techniques involving the use of a SiO.sub.2 film formed by a sputtering method and a silicon nitride (e.g., Si.sub.3 N.sub.4) film formed by a plasma method (or glow discharge method) for the outer protection film for the interconnection layers. This development has been found to be preferable to the hitherto known silicon oxide film (SiO.sub.2 or PSG film) which usually contains phosphorus (P). In such case, the Poly Si resistance element having a Si.sub.3 N.sub.4 film deposited thereon will undergo a remarkable variation in the resistance value as illustrated by a curve 42 in FIG. 4 when subjected to the hydrogen annealing process. On the other hand, when a sputtered SiO.sub.2 film is to be used, the resistance value of the Poly Si element will be decreased considerably immediately after the deposition of SiO.sub.2 film. Such decrease in the resistance value can be compensated to some degree through the subsequent hydrogen annealing process as illustrated by a curve 43. However, restoration of the resistance to the desired value can not be attained.
It is believed that the Poly Si resistance element is susceptible to electrical damage due to plasma and likely to undergo variations in the electrical characteristic by reason of possible contamination of the Si.sub.3 N.sub.4 film. Such variation in the electrical characteristic or property seems to be similar in genesis mechanism to the one observed usually in a conventional MOS transistor placed in a discharging plasma. However, it has been found that, in the case of the memory cell described above, the electrical characteristic such as the threshold voltage value of MOS transistors remains in the range of the standard value even after the hydrogen annealing process.
In the light of the foregoing, it is believed that the deposited Poly Si film will undergo variation in respect of the conductivity thereof due to undesirable fixed charges and surface states produced at the interface between the Poly Si film and an insulation film under the influence of plasma and contamination even in the degree which can be neglected in the case of MOS transistor formed in a single crystal substrate.
Referring to FIG. 5 which shows in a top plan view a pattern of a memory cell device corresponding to the one shown in FIG. 1 and including the Poly Si resistance element, numeral 50 denotes an Al metallization for earth connection, 51 and 52 denote data lines realized by Al metallization, 53 denotes a diffusion layer, 54 denotes a word line realized by a Poly Si interconnection layer, 55, 56 and 57 designate contacting parts, and 58, 59 and 60 denote low resistance interconnection layers formed of n.sup.+ -conductivity type. Poly Si. As can be seen from the drawing, the Al metallization layer 51 serving as the data line extends over one (A in the illustrated structure) of two high resistance Poly Si layer parts A and B. A sectional view of the part A of the high resistance Poly Si layer as well as the adjacent regions is schematically shown in FIG. 6. Since the potential at the Al metallization layer 51 serving as the data line is increased to a level in approximation to the supply voltage level (e.g. 5 V), a channel will be formed to the high resistance Poly Si part A underlying the Al metallization layer 51 due to parasitic MOS (Metal-Oxide-Semiconductor) effect, thereby to increase remarkably the current flow in the high resistance Poly Si part A, which is of course undesirable from the view point of power dissipation. In FIG. 6, reference numeral 61 denotes a SiO.sub.2 film, 62 a PSG film and 63 designates a substrate of Si.
FIG. 7 graphically illustrates variation in the small current flowing through the high resistance Poly Si layer described above as a function of a gate voltage at an Al gate electrode formed on the high resistance Poly Si layer with the interposition of a PSG film of about 0.8 .mu.m in thickness. As can be seen from this figure, when the gate voltage at the Al gate electrode increases beyond a predetermined voltage (about 4 V in the example shown in FIG. 7), the current flowing through the high resistance Poly Si will increase, which can be explained by the fact that a channel is formed at the surface of the high resistance Poly Si layer underlying the PSG film due to the parasitic MOS effect under the influence of the gate potential at the Al gate electrode. Such parasitic MOS effect is of course disadvantageous in that the power dissipation in the memory cell is undesirably increased. Particularly, when a nitride film is additionally formed as an outer protection layer on the PSG film by a plasma deposition method, the level of the gate voltage at which the current flowing through the high resistance Poly Si layer begins to increase will tend to be lowered, whereby the use of the nitride film formed by the plasma deposition method is eventually rendered impractical.
The other part B of the high resistance Poly Si layer shown in FIG. 5 has no Al metallization layer extending thereon but is deposited directly only with a PSG film, as is illustrated in a sectional view shown in FIG. 8. However, when the nitride (Si.sub.3 N.sub.4) film is formed over the Al metallization layer through the interposition of PSG film by a plasma method, the resistance value of the Poly Si part B underlying the Si.sub.3 N.sub.4 film is decreased as in the case of the Poly Si part A described above, involving disadvantageously a correspondingly increased power dissipation.